Is it possible to design an expanding opcode to allow the following to be encoded in a 16 bit instruction? we have registers R0 to R7 14 instructions with 3 registers 255 instructions with two registers 512 instructions with one register
The law of diminishing returns (also law of diminishing marginal returns or law of increasing relative cost) states that in all productive processes, adding more of one factor of production, while holding all others constant (\"ceteris paribus\"), will at some point yield lower per-unit returns here if computer wird size increses speed increses at beginning and stops at somepoint if we go on incresaung size of registers the all process become slow due to large size of registers so speed decreases